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5.2.3.2 Access Performance
The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth
of 4x a single AHB interface.
The Bus Matrix accepts new transfers to be initiated by each master in each cycle without inserting any
wait-states. However, the slaves may insert wait-states depending on their internal throughput and the
clock frequency.
The Cortex-M3 and the DMA Controller, and the peripherals (not peripherals in the low frequency clock
domain) run on clocks which can be prescaled separately. When accessing a peripheral which runs on
a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition
to master arbitration, is given by:
Memory Wait Cycles with Clock Equal or Faster than the HFCORECLK
N cycles = 2 + N slave cycles
(5.3)
where N slave cycles is the wait cycles introduced by the slave.
When accessing a peripheral which runs on a slower clock than the HFCORECLK, wait cycles are
introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per
access, in addition to master arbitration, is given by:
Memory Wait Cycles with Clock Slower than the CPU
N cycles = (2 + N slave cycles ) x f HFCORECLK /f HFPERCLK
(5.4)
where N slave cycles is the wait cycles introduced by the slave.
Clocks and prescaling are described in more detail in Chapter 11 (p. 92) .
5.3 Access to Low Energy Peripherals (Asynchronous Registers)
5.3.1 Introduction
The Low Energy Peripherals are capable of running when the high frequency oscillator and core system
is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to
perform tasks while the system energy consumption is minimal.
The Low Energy Peripherals are:
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Liquid Crystal Display driver - LCD
Low Energy Timer - LETIMER
Low Energy UART - LEUART
Pulse Counter - PCNT
Real Time Counter - RTC
Watchdog - WDOG
All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low
Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints
on how register accesses are performed, as described in the following sections.
5.3.1.1 Writing
Every Low Energy Peripheral has one or more registers with data that needs to be synchronized
into the Low Energy clock domain to maintain data consistency and predictable operation. Due to
2011-04-12 - d0001_Rev1.10
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